The present invention relates generally to the field of semiconductor electronics, and more particularly to graphene field-effect transistors.
Field-effect transistors (FETs) can be semiconductor devices fabricated on a bulk semiconductor substrate or on a silicon-on-insulator (SOI) substrate. FET devices generally consist of a source, a drain, a gate, and a channel between the source and drain. The gate is separated from the channel by a thin insulating layer, typically of silicon oxide, called the gate oxide. A voltage applied between the source and gate induces an electric field that modulates the conductivity of the channel between the source and drain thereby controlling the current flow between the source and the drain. Current integrated circuit designs use complementary metal-oxide-semiconductor (CMOS) technology that use complementary and symmetrical pairs of p-type and n-type metal oxide semiconductor field-effect transistors (MOSFETs) for logic functions.
Graphene is a single atomic layer of carbon that exhibits exceptional electronic properties, such as a relative high carrier mobility and saturation velocity. These exceptional properties enable graphene to be used to form graphene field-effect transistors (GFETs), which may be useful in applications up to the terahertz frequency region. A typical GFET includes a source contact and a drain contact with a graphene sheet extending between them to form a channel that is gated. The GFET operates, in part, by modulating the conductance of the graphene sheet, usually via a gate metal proximate the graphene sheet separated by a dielectric.